1. Field of the Invention
The present invention relates to a reference voltage generation circuit and a bias circuit formed by using a BiFET process and, more particularly, to a reference voltage generation circuit and a bias circuit capable of suppressing a variation in gain due to a process variation.
2. Background Art
Conventional GaAs-FET power amplifiers have a negative threshold voltage and therefore have the drawback of requiring a negative gate bias voltage. In contrast, GaAs heterojunction bipolar transistor (GaAs-HBT) power amplifiers require no negative gate bias voltage, are capable of single power supply operation and have more uniform device characteristics in comparison with FET power amplifiers. For this reason, use of GaAs-HBT power amplifiers in CDMA portable telephones, wireless LAN devices, etc., has been markedly increased (see, for example, US2007/0159145-A1 and Japanese Patent Laid-Open No. 2004-343244).
A BiFET process for making a FET together with a GaAs-HBT on one substrate has recently been applied to products. Ordinarily, in a GaAs BiFET process, an HBT and a depletion mode (normally on) FET are mounted. Further, a process in which an enhancement-mode (normally off) FET is made in addition to an HBT and a depletion mode FET on one substrate has recently been reported in the learned circle (IEEE: Radio Frequency Integrated Circuits Symposium 2008).